It is now well established that the performance of n-MOSFETs fabricated in a Si-containing layer under biaxial tensile strain is enhanced compared to that of devices of comparable size fabricated in unstrained Si-containing, e.g., either in bulk Si or in SOI substrates. The magnitude of the n-MOSFET performance enhancement increases with increasing biaxial tensile strain in the Si. This finding is reported, for example, in K. Rim, et al., 2002 Symposium on VLSI Technology Digest of Technical Papers, 98 (2002).
It has also been demonstrated that the performance of p-MOSFETs is degraded compared to that of the same size device fabricated in bulk Si or SOI for values of the biaxial tensile strain less than about 1%. This is illustrated in FIGS. 1A and 1B; FIG. 1A provides data for electron mobility, while FIG. 1B provides data for hole mobility.
However, for values of biaxial tensile strain greater than about 1%, the performance of the p-MOSFET is significantly enhanced compared to that of p-MOSFETS of similar size fabricated in an unstrained Si-containing material. Thus, a method to produce a Si-containing material under biaxial tensile strain of less than about 1% only in regions of the wafer where the n-MOSFETs will be fabricated and not in regions of the wafer where the p-MOSFETs will be fabricated is needed.
Several different methods to produce a Si-containing layer under biaxial tensile strain over the entire wafer surface have been implemented. These methods typically employ a strain-relaxed SiGe buffer layer that serves as a “virtual substrate” for the epitaxial growth of a pseudomorphic Si-containing layer under biaxial tensile strain. The degree of biaxial tensile strain in the Si-containing layer is determined by the alloy composition and degree of strain relaxation of the SiGe buffer layer. Because strain relaxation of the SiGe buffer layer typically occurs by the introduction of 60° misfit dislocations, great care must be taken when fabricating the SiGe buffer layer to minimize the threading arms associated with these misfit dislocations. The threading dislocations extend to the wafer surface where the devices are, and thus may degrade device performance.
The most commonly used SiGe virtual substrate consists of a very thick (several μm) SiGe layer in which the alloy composition is increased continuously, or in steps, up to the required value, followed by another very thick (several μm) layer of the desired uniform alloy composition. Such thick graded buffer layers have been shown to have a low density of threading dislocations and are thus potentially suitable for CMOS applications. See, for example, F. K. LeGoues, et al., J. Appl. Phys. 71, 4230 (1992); U.S. Pat. No. 5,659,187 to F. K. LeGoues, et al.; E. A. Fitzgerald, et al., Appl. Phys. Lett. 59, 811 (1991); and G. Kissinger, et al., Appl. Phys. Let. 66, 2083 (1995).
An alternative method of fabricating a strain-relaxed SiGe buffer layer using ion implantation of He or other atoms to introduce dislocation nucleation sources in a controlled manner has also been implemented. This particular approach of using He ion implantation is described, for example, in S. H. Christiansen, et al. Mat. Res. Soc. Symp. Proc. 686, 27-32 (2002); M. Luysberg, et al., J. Appl. Phys. 92, 4290 (2002); J. Cai, et al., J. Appl. Phys. 95, 5347 (2004) and Mat. Res. Soc. Symp. Proc. 809, B8.2 (2004); D. Buca, et al., Mat. Res. Soc. Symp. Proc. 809, B1.6 (2004) and references therein; U.S. Pat. Nos. 6,593,625 and 6,709,903 to S. H. Christiansen, et al.; and U.S. application Ser. No. 10/299,880, filed Nov. 19, 2002.
In the ion implantation approach, a thin pseudomorphic or nearly pseudomorphic SiGe layer under biaxial compressive strain is first grown on a Si-containing substrate. He or other atoms are then implanted into this SiGe/Si-containing heterostructure. The implantation energy is chosen so that the projected range of the implanted He lies about 200 nm below the SiGe/Si interface. The wafer is then annealed in a furnace in a He or a N2 atmosphere at temperatures above 700° C. for at least 10 minutes. He-induced bubbles or platelets are formed during annealing. These defects are nucleation sources for misfit dislocations that relieve about 70-80% of the compressive strain, depending on the thickness of the SiGe layer. The threading dislocation density in these SiGe buffer layers was found to correlate with the amount of He implanted into the SiGe layer; see J. Cai, et al., J. Appl. Phys. 95, 5347 (2004). For a given He dose, there is a minimum density for thinner SiGe layers and when the implanted atoms are relatively deep, but still close enough to the surface, that the SiGe layer relaxes (see FIG. 2). The degree of strain relaxation increases with the thickness of the SiGe layer indicating that the SiGe layer should be as thick as possible for each alloy composition.
Little or no strain relaxation occurs in wafers that are not implanted and, which were annealed under the same conditions as the implanted wafers (see FIGS. 3A and 3B). Finally, the device structure is completed by the epitaxial growth of an additional SiGe layer of the same alloy composition as the relaxed SiGe buffer layer or with the alloy composition chosen so that the in-plane lattice parameter is matched to that of the 70-80% strain-relaxed SiGe layer followed by a thin pseudomorphic Si-containing layer which is under biaxial tensile strain. The thickness of the resulting implanted and annealed SiGe buffer layer may be as little as 10% of the thickness of the graded SiGe buffer layer and has a comparable threading dislocation density and a smoother surface. This prior art method also offers the advantage of lowering the cost of device fabrication.
However, in view of the degraded performance of p-MOSFETs fabricated in Si-containing layers under biaxial tensile strain of <1%, further improvements are needed. Specifically, a new and improved method for fabricating structures including a strain-relaxed SiGe virtual substrate and a Si-containing layer under biaxial tensile strain only in areas of the wafer where the n-MOSFETS are to be fabricated and a different layer structure in areas of the wafers where the p-MOSFETs are to be fabricated is desirable.